1. Field of Invention
The present invention relates to a pulse width modulation neuron circuit. More particularly, the present invention relates to pulse width modulation neuron circuit, in which its output pulse width realizes a sigmoid activation function of its voltage input, and power-down of some circuits of the neuron circuit in pulse interval will reduce the power assumption significantly.
2. Description of Related Art
As the most important block in the artificial neural network (ANNs), the behavior of the neuron has vast influence on the performance of the whole network. The sigmoid function is adopted as the activation function of artificial neuron popularly. Pulse stream approach is often used to realize the neuron with this function, which has a digital stream output as an analog information axis. There have been several kinds of pulse stream neuron circuits. Other existed circuits have various kinds of limitations, such as sensitivity to noise due to narrow dynamic range, and bulky size due to the complicated voltage integrator circuit and the operational amplifier in them. Furthermore, all these neuron circuits are not power-optimized.
The invention provides a novel compact pulse width modulation (PWM) neuron circuit, in which its output pulse width realizes a sigmoid activation function of its voltage input.
The invention provides a novel compact pulse width modulation (PWM) neuron circuit, in which the power-down of some circuits in pulse interval will reduce the power assumption greatly.
As embodied and broadly described herein, the invention provides a pulse width modulation (PWM) neuron circuit including an input control circuit, a charge/discharge circuit and an output control circuit. The input control circuit is coupled to an input voltage source and an operation voltage source. The charge/discharge circuit is coupled to the current mirror circuit. The output control circuit is being coupled to the charge/discharge circuit and the input control circuit. The input control circuit is activated and controlled by the output control circuit and a first current is generated from the input control circuit in accordance with the input voltage source and the operation voltage source. The charge/discharge circuit is charged to a predetermined voltage level in accordance with the first current from the input control circuit. The predetermined voltage level is sufficient enough to make an output of the output control circuit being changed with logic status of the output.
In the above-mentioned pulse width modulation (PWM) neuron circuit, further includes a current mirror circuit. The current mirror circuit is interposed between the input control circuit and the charge/discharge circuit. The first current of the input control circuit is mirrored by a second current generated by the charge/discharge circuit.
In the above-mentioned pulse width modulation (PWM) neuron circuit, the charge/discharge circuit comprises a capacitor and a first transistor. The capacitor is charged by the second current and discharged when the first transistor being turned on.
In the above-mentioned pulse width modulation (PWM) neuron circuit, the first transistor is controlled by the output of the output control circuit.
In the above-mentioned pulse width modulation (PWM) neuron circuit, the input control circuit comprises a second transistor. A gate of the second transistor is coupled to and controlled by the output of the output control circuit.
In the above-mentioned pulse width modulation (PWM) neuron circuit, the input control circuit further comprises a third transistor (M1), one of a pair of source/drain regions of the third transistor being coupled to one of a pair of source/drain regions of the second transistor; a forth transistor (M2), one of a pair of source/drain regions of the forth transistor being coupled to the other of the source/drain regions of the third transistor and the first current; a fifth transistor (M3), one of a pair of source/drain regions of the fifth transistor being coupled to the other of the source/drain regions of the forth transistor and being coupled to a gate of the fifth transistor and a gate of the third transistor, the other source/drain region of the fifth transistor being coupled to the operation voltage source; and a sixth transistor, one of a pair of source/drain regions of the sixth transistor being coupled to a gate of the forth transistor and the other source/drain region of the fifth transistor being coupled to the input voltage source, a gate of the fifth transistor being coupled to the operation voltage source.
In the above-mentioned pulse width modulation (PWM) neuron circuit, the output control circuit comprises a 3-port NOR gate. The 3-port NOR gate controls the output of the output control circuit. One port of the 3-port NOR gate is coupled to a operation clock signal. One port of the 3-port NOR gate is coupled to the capacitor. When the operation clock signal is on a logic high status, the output of the output control circuit is changed its logic status when the capacitor is charged to or over the predetermined voltage level.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.